Faculty:

• Milos Ercegovac

Visitors:

• Prof. Jean Claude Bajard, University of Montpellier, France.
• Dr. Aksenti Grnarov, University of Skopje, Macedonia.
• Dr. Gerben Hekstra, Technical University, Delft, The Netherlands.
• Prof. Zoran Jovanovic, University of Belgrade, Serbia.
• Dr. Zoran Konstantinovic, Institute M. Pupin, Belgrade, Serbia.
• Prof. Paolo Montuschi, Politecnico di Torino, Italy.
• Dr. Jean-Michel Muller, Ecole Normal Superieure, Lyon, France.
• Prof. Metin Ozbilen, Turkey
  
• Dr. Alejandro Pineiro, University of Santiago de Compostela, Spain.
• Dr. Arnaud Tisserand, University of Montpellier, France.
• Dr. Dong Wang, Tsinghua University, Beijing, China.
  

Graduate Students:

• Pouya Dormiani
• Seok Won Heo
  
• Gabriel (Seung Huyn) Pan
• Hojat Parta

Alumni (Ph.D.):

• Z. Huang, High-Level Optimization Techniques for Low-Power Multiplier Design, 2003.
• R.D. McIlhenny, Complex Number On-line Arithmetic for Reconfigurable Hardware: Algorithms, Implementations, and Applications, 2002. 
• A.F. Tenca, Variable Long-Precision Arithmetic (VLPA) for Reconfigurable Architectures, 1998.
• J. Harding,  virtualRAID: A Mass Storage Architecture for Out-of-Core Applications, (co-chair with L. McNamee), 1997.
• D.R. Greening, Simulated Annealing With Errors, 1995.
• R. Dionysian, Variable-Precision Arithmetic for Vector Quantization, 1994.
• M. E. Louie, Variable Precision Arithmetic with Lookup Table Based Field Programmable Gate Arrays, 1994.
• J. H. Liu, A Synthesis System for Application Specific Arrays Implementing Matrix Computations, 1994.
• J. S. Fernando, Design Alternatives for Recursive Digital Filters Using On-Line Arithmetic, 1993.
• S.-L. Lu, Asynchronous Arithmetic Structures in Differential CMOS, 1992.
• C. Kesselman, Integrating Performance Analysis with Performance
  Improvement in Parallel Programming, 1991.
• P. K.-G. Tu,  On-Line Arithmetic Algorithms for Efficient Implementation, 1990.
• D. R. Patel, An Applicative Framework for Hardware Synthesis, 1990.
• L. Alkalaj, Architectural Support for Concurrent Logic Programming Languages,
  (co-chair with T. Lang), 1989.
• R. Brackert,  Design and Implementation of A High Speed Recursive Digital Filter Using On-Line Arithmetic, (co-chair with A.N. Wilson, Jr.), 1989.
• M. M. Takata, Interval-based Timing Simulation Using A Graph Model of Timing Behavior (GMTB), 1987.
• S. Kelem, A Method For The Automatic Translation of Algorithms From A High-Level Language Into Integrated Circuits, (co-chair with B. Bussell), 1987.
• P. Chan,  On Concurrent Architectures For Simulation of Large-Scale Integrated Digital Circuits, (co-chair with M. Aoki), 1987.
• A. Kapelnikov, Analytic Modeling Methodology For Evaluating the Performance of Distributed Multiple-Computer Systems, (co-chair with R.M. Muntz, 1987.
• M.D.F. Schlag, Layout From A Topological Description, (co-chair with S. Greibach), 1986.
• J. Arabe,  Compiler Considerations and Run-Time Storage Management For A Functional Programming System, 1986.
• J.L. Gaudiot, Partitioning, Allocation and Scheduling Issues for a Class of Dataflow Multiprocessors, 1982.
• V. Oklobdzija, Design for Testability of VLSI Structures Through The Use of Circuit Techniques, 1982.
• O. Watanuki, Floating-Point On-Line Arithmetic For Highly Concurrent Digit-Serial Computation: Application to Mesh Problems, 1981.
• A. Gorji-Sinaki,  Error-Coded Algorithms For On-Line Arithmetic, 1981.

• D. Lander,  Square Root using Limited Precision Primitive Operations,  2006 (co-Chair W. Kaiser, EE Department)
• D. Omoto, Computing Inference in Bayesian Networks using a Reconfigurable System, 2005 (co-Chair W. Kaiser, EE Department)
• E.G. Benowitz, Reducing the Latency of Division Operations with Partial Caching, 2002.
• A. Schneider, BigSky: An On-Line Arithmetic Circuit Generation System,  1999.
• D. Le, MAMACG: A Tool for Automatic Mapping of Matrix Algorithms into Mesh Array Computational Graphs, 1993.
• W. Wu,  FLAG: An FP based VLSI Layout Generator, 1989.
• D. Greening, Granularity in Manchester Dataflow Programs, 1988.
• A. Dianysian,  Acknowledgement Arc Removal in Data Flow Graphs, 1987,
• A. Mazer,  APL Implementation on a Message-based Multiprocessor, 1987,
• D. M. Tullsen,  A Very Large Scale Integration Implementation of an On-Line Arithmetic Unit, June 1986, Report No. CSD-860094.
• T.M. Ravi, Partitioning and Allocation of Functional Programs  for Data Flow Processors, April 1986, Report No. CSD-860063.
• M. Louie, A Distributed Functional Programming Interpreter, 1986.
•  L. Alkalaj, A Uniprocessor Implementation of the FP Functional Language, 1986, (co-chair T. Lang), Report No. CSD-860064.
• J. Worley, A Functional Style Description of Digital Systems, 1986, CSD-860054.
• F. Meshkinpour, On Specification and Design of Digital Systems  Using an Applicative Hardware Description Language, 1984, Report No. CSD-840046.
• S.L. Lu, A Compiler for a Functional Programming System, 1984, Report No. CSD-840045.
• P. Chan, A Dataflow Multiprocessor: Programming, Simulation and Performance Prediction, 1984, Report No. CSD-840044.
• F. Xiong, A Functional Language Machine Based on Queues,  1984, Report No. CSD-840047.
• J. Kellman, Concurrent Execution of Functional Languages, 1982.
• Y. Afek, Firmware Specification and Its Silicon Translation, 1982.
• F. Tong, Implementation of Optimizing Pipelines for Data Flow Programs, 1981.
• M. Dadseresht, Design Rule Checking and Verification Based on MOS/LSI Mask Information, 1981.
• B. Hunt, Logic Design Simulation: A Language, Interpeter and Simulator, June 1981.
• G. Karimi, On VLSI-Oriented Partitioning of Interconnection Networks for Multi-Microcomputer Systems,  1981.
• D. Patel,  A System Organization for Applicative Programming, 1980.
• D. Lahti, Applications of a Functional Programming Language to Hardware Synthesis, 1980.
• B. Brode, An Analysis of a High-Performance System: Potential Improvements to the CRAY-I,  1980.
• G. Fucik, Automated Design of Special-Purpose Processors, 1980.
• M. Feller,  A Parallel Queue Organization for High-Speed Computing, 1980.
• M.C. Chu, A Multi-Microprocessor Bit-Slice Organization for  Function Evalution, 1979,
• M.M. Takata,  A Design of Modular Arithmetic Unit for Polynomial and Rational Function Evaluation, 1978.
• V.G. Oklobdzija, An On-Line Higher Radix Square Rooting Algorithm,  1978.