People affiliated with the
Digital Arithmetic and Reconfigurable Architecture Laboratory
Prof. Jean Claude Bajard, University of Montpellier, France.
Dr. Aksenti Grnarov, University of Skopje, Macedonia.
Dr. Gerben Hekstra, Technical University, Delft, The Netherlands.
Prof. Zoran Jovanovic, University of Belgrade, Serbia.
Dr. Zoran Konstantinovic, Institute M. Pupin, Belgrade, Serbia.
Prof. Paolo Montuschi, Politecnico di Torino, Italy.
Dr. Jean-Michel Muller, Ecole Normal Superieure, Lyon, France.
Prof. Metin Ozbilen, Turkey
Dr. Alejandro Pineiro, University of Santiago de Compostela, Spain.
Dr. Arnaud Tisserand, University of Montpellier, France.
Dr. Dong Wang, Tsinghua University, Beijing, China.
Seok Won Heo
Gabriel (Seung Huyn) Pan
High-Level Optimization Techniques for Low-Power Multiplier Design,
Complex Number On-line Arithmetic for Reconfigurable Hardware: Algorithms, Implementations, and Applications
Variable Long-Precision Arithmetic (VLPA) for Reconfigurable Architectures,
virtualRAID: A Mass Storage Architecture for Out-of-Core Applications
, (co-chair with L. McNamee), 1997.
Simulated Annealing With Errors
Variable-Precision Arithmetic for Vector Quantization
M. E. Louie,
Variable Precision Arithmetic with Lookup Table Based Field Programmable Gate Arrays
J. H. Liu,
A Synthesis System for Application Specific Arrays Implementing Matrix Computations
J. S. Fernando,
Design Alternatives for Recursive Digital Filters Using On-Line Arithmetic
Asynchronous Arithmetic Structures in Differential CMOS
Integrating Performance Analysis with Performance
Improvement in Parallel Programming
P. K.-G. Tu,
On-Line Arithmetic Algorithms for Efficient Implementation
D. R. Patel,
An Applicative Framework for Hardware Synthesis
Architectural Support for Concurrent Logic Programming Languages
(co-chair with T. Lang), 1989.
Design and Implementation of A High Speed Recursive Digital Filter Using On-Line Arithmetic
, (co-chair with A.N. Wilson, Jr.), 1989.
M. M. Takata,
Interval-based Timing Simulation Using A Graph Model of Timing Behavior (GMTB)
A Method For The Automatic Translation of Algorithms From A High-Level Language Into Integrated Circuits
, (co-chair with B. Bussell), 1987.
On Concurrent Architectures For Simulation of Large-Scale Integrated Digital Circuits,
(co-chair with M. Aoki), 1987.
Analytic Modeling Methodology For Evaluating the Performance of Distributed Multiple-Computer Systems
, (co-chair with R.M. Muntz, 1987.
Layout From A Topological Description
, (co-chair with S. Greibach), 1986.
Compiler Considerations and Run-Time Storage Management For A Functional Programming System
J.L. Gaudiot, Partitioning,
Allocation and Scheduling Issues for a Class of Dataflow Multiprocessors
Design for Testability of VLSI Structures Through The Use of Circuit Techniques
Floating-Point On-Line Arithmetic For Highly Concurrent Digit-Serial Computation: Application to Mesh Problems
Error-Coded Algorithms For On-Line Arithmetic
D. Lander, Square Root using Limited Precision Primitive Operations, 2006 (co-Chair W. Kaiser, EE Department)
Computing Inference in Bayesian Networks using a Reconfigurable System
, 2005 (co-Chair W. Kaiser, EE Department)
Reducing the Latency of Division Operations with Partial Caching
BigSky: An On-Line Arithmetic Circuit Generation System
D. Le, MAMACG: A Tool for Automatic Mapping of Matrix Algorithms into Mesh Array Computational Graphs, 1993.
FLAG: An FP based VLSI Layout Generator,
Granularity in Manchester Dataflow Programs
Acknowledgement Arc Removal in Data Flow Graphs
APL Implementation on a Message-based Multiprocessor,
D. M. Tullsen,
A Very Large Scale Integration Implementation of an On-Line Arithmetic Unit
, June 1986, Report No. CSD-860094.
Partitioning and Allocation of Functional Programs for Data Flow Processors
, April 1986, Report No. CSD-860063.
A Distributed Functional Programming Interpreter
A Uniprocessor Implementation of the FP Functional Language
, 1986, (co-chair T. Lang), Report No. CSD-860064.
A Functional Style Description of Digital Systems
, 1986, CSD-860054.
On Specification and Design of Digital Systems Using an Applicative Hardware Description Language,
1984, Report No. CSD-840046.
A Compiler for a Functional Programming System,
1984, Report No. CSD-840045.
A Dataflow Multiprocessor: Programming, Simulation and Performance Prediction
, 1984, Report No. CSD-840044.
A Functional Language Machine Based on Queues
, 1984, Report No. CSD-840047.
Concurrent Execution of Functional Languages
Firmware Specification and Its Silicon Translation,
Implementation of Optimizing Pipelines for Data Flow Programs
Design Rule Checking and Verification Based on MOS/LSI Mask Information,
Logic Design Simulation: A Language, Interpeter and Simulator
, June 1981.
On VLSI-Oriented Partitioning of Interconnection Networks for Multi-Microcomputer Systems
A System Organization for Applicative Programming
Applications of a Functional Programming Language to Hardware Synthesis
An Analysis of a High-Performance System: Potential Improvements to the CRAY-I
Automated Design of Special-Purpose Processors,
A Parallel Queue Organization for High-Speed Computing
A Multi-Microprocessor Bit-Slice Organization for Function Evalution,
A Design of Modular Arithmetic Unit for Polynomial and Rational Function Evaluation
An On-Line Higher Radix Square Rooting Algorithm
Links to Computer Science Department