Digital Arithmetic and Reconfigurable Architecture Laboratory People

Research and Projects
Digital Arithmetic and Reconfigurable Architecture Laboratory

Algorithms and Architectures for Computing Inferences in Bayesian Networks
Complex Arithmetic Algorithms and Implementations (with Jean-Michel Muller, ENS, Lyon, France)
Modular Reduction and Inversion (with Jean-Claude Bajard, LIRRM, Montpellier, France)
Online Arithmetic Approach to Floating-Point Operations on Massively Parallel Fixed-Point Units
(supported by California MICRO and STMicroelectronics)

Past Projects:

Reducing the Latency of Division Operation, MICRO - Fujitsu Labs, 2001.
Reconfigurable Hardware for Numerically Intensive Computations, MICRO - Raytheon Systems and Xilinx, 1998-2000.
Effect of Redundancy in Arithmetic Operations on Processor Cycle Time, Architecture and Implementation, with T. Lang, UCI, NSF Grant, 1998 - 2000.
Arithmetic Algorithms and Structures for Low-Power Systems, with T. Lang, UCI, NSF Grant, 1994-1998.
Variable-Precision Arithmetic Structures and Algorithms for Field-Programmable Gate Arrays, MICRO - Xilinx & Virtual Computer Company, 1996-1997.
Arithmetic Algorithms and Structures for Low-Power Systems, with T. Lang, UC Irvine, NSF Grant, 1994-1997.
On-Line Arithmetic: From Theoretical Studies to Practical Implementation, NSF-CNRS France, 1993-1996.
Arithmetic Structures and Algorithms for FPGAs, MICRO - Xilinx, 1992-1993.
Field-Programmable Application-Specific Processor Arrays, MICRO - Xilinx, 1991-1992.
On-Line Arithmetic Algorithms for VLSI Design of Recursive Filters, MICRO - Rockwell, 1990-1991.
Design of Mesh Arrays for Matrix Computations, MICRO - Hughes Aircraft Company, 1990-1991.
Flexible Floating-Point Modules for Wafer Scale Integration, MICRO - TRW, 1989-1990.
Composite Operations Using On-Line Arithmetic for Application-Specific Parallel Architectures: Algorithms, Designs, and Experimental Studies, with T. Lang, NSF Grant, 1989-1993.
On-Line Arithmetic Algorithms for VLSI Design, MICRO - Rockwell, 1988-1989.
Effect of Nonuniform Traffic on Multistage Interconnection Networks for Multiprocessors, with T. Lang, MICRO - Hughes Aircraft Company, 1987-1988.
Concurrent Architectures and Algorithm Mapping in Digital Signal Processing, MICRO - Hewlett Packard, 1987-1988.
On-Line Algorithms and Structures for VLSI, Office of Naval Research, 1984-1987.
Multiprocessing System Evaluation and Programming Environment, Sandia National Labs, 1984-1985.
Specification and Design Methodologies for High-Speed
Fault-Tolerant Array Algorithms and Structures in VLSI, with A. Avizienis, Office of Naval Research, 1983-1986.
A Data Flow Multi-Purpose Processor for High Speed Digital Simulation, with W. Karplus, NASA, 1982-1984.
A High Level Language Approach to Custom Chip Layout Design, MICRO/Rockwell, 1982-1985.
Data Flow Computing Approach in High-Speed Digital Simulation, with W. Karplus, NASA, 1980-1982.
Research in Distributed Processing, with A. Avizienis, Office of Naval Research, 1979-1983.
Fault-Tolerant Computing, with A. Avizienis, NSF Grant, 1975-1978.