Digital Arithmetic and Reconfigurable Architecture Laboratory Publications

Publications by the
Digital Arithmetic and Reconfigurable Architecture Laboratory

Books

Digital Arithmetic, M.D. Ercegovac and T. Lang, Morgan Kaufmann, An Imprint of Elsevier, 2004.

Introduction to Digital Systems, M.D. Ercegovac, T. Lang and J. Moreno, New York, NY: John Wiley & Sons, 1999.

Division and Square Root: Digit-Recurrence Algorithms and Implementations. M.D. Ercegovac and T. Lang.
Norwell, MA: Kluwer Academic Publishers, pps. 230, 1994.

Digital Systems and Hardware/Firmware Algorithms. M.D. Ercegovac and T. Lang. New York: J. Wiley & Sons, 1985.

Papers and Reports

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2008:

An Efficient Method for Evaluating Complex Polynomials. M.D. Ercegovac and J.-M. Muller, Journal of Signal Processing Systems, Springer, published online, http://www.springerlink.com/content/5582844402n0t2x1/, September 24, 2008.
Design and FPGA Implementation of Radix-10 Algorithm for Division with Limited Precision Primitives. M.D. Ercegovac and R. McIlhenny, Proc. 42nd Asilomar Conference on Signals, Systems and Computers, pp. 1-5, 2008.
Design and Implementation of Complex Multiply Add and Other Similar Operators. P. Dormiani and M.D. Ercegovac,
Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XVIII, Vol. 7074, 12 pps., 2008.
An Efficient Method for Evaluating Polynomial and Rational Function Approximations. N. Brisebarre, S. Chevillard, M. D. Ercegovac, J.-M. Muller and S. Torres. IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 233-238, July 2008.

2007:

Complex Square Root with Operand Prescaling. M.D. Ercegovac and J.-M. Muller,
Journal of VLSI Signal Processing, 49:19–30, 2007.
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. T.Y. Yeh, P. Faloutsos, M.D. Ercegovac, S.J. Patel, and G. Reinman. 40th Annual IEEE/ACM International Symposium on Microarchitectures, MICRO-07, pp. 394-406, 2007.
A Design Method for Heterogeneous Adders. J-G. Lee, J-A. Lee, B-S. Lee, and M.D. Ercegovac, Proc. ICESS 2007, Lecture Notes in Computer Science 4532, pp. 121-132, Springer-Verlag, 2007.
On Digit-by-Digit Methods for Computing Certain Functions. M.D. Ercegovac.
Proc. 41st Asilomar Conference on Signals, Systems and Computers, pp. 338-342, 2007.
ISA Extensions for Online Floating-Point Addition. P. Dormiani and M.D. Ercegovac,
Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XII, Vol. 6697, 12 pps., 2007.
Complex Multiply-Add and Other Related Operators. M.D. Ercegovac and J.-M. Muller,
Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XII, Vol. 6697, 12 pps., 2007.
A Hardware-Oriented Method for Evaluating Complex Polynomials. M.D. Ercegovac and J.-M. Muller,
IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 122-127, 2007.

2006:

Omnipresence of Tesla's Work and Ideas. M.D. Ercegovac,
6th International Symposium Nikola Tesla, pp. 251-56, October 2006.
Arithmetic Processor for Solving Tridiagonal Systems of Linear Equations. M.D. Ercegovac and J.-M. Muller,
Proc. 40th Asilomar Conference on Signals, Systems and Computers, pp. 337-340, 2006.
Interconnection Scheme for Networks of Online Modules. P. Dormiani and M.D. Ercegovac,
Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XII, pp. 631308-1:12, 2006.
On the Design of an On-line Complex Householder Transform. R. McIlhenny and M.D. Ercegovac,
Proc. 40th Asilomar Conference on Signals, Systems and Computers, pp. 318-322, 2006.
Study of RNS representation and modular products summation. J.C. Bajard, S. Duquesne, M. Ercegovac, and N. Meloni,
Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XII, pp. 631304-1:11, 2006.

2005:

High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. J.-A. Pineiro, M.D. Ercegovac,
and J.D. Bruguera. Journal of VLSI Signal Processing, Vol.40, pp.109-123, 2005.
High-Performance Low-Power Left-to-Right Array Multiplier Design. Z. Huang and M.D. Ercegovac. IEEE Trans. Computers, 54(3):272-283, 2005.
Simple Seed Architectures for Reciprocal and Inverse Square Root. M. D. Ercegovac, J.-M. Muller, A. Tisserand,
Proc. 39th Asilomar Conference on Signals, Systems and Computers, 5 pps., 2005.
On the Design of an On-line Complex Matrix Inversion Unit. R. McIlhenny and M. D. Ercegovac,
Proc. 39th Asilomar Conference on Signals, Systems and Computers, 5 pps., 2005.
A Design of Online Scheme for Evaluation of Multinomials. P. Dormiani, D. Omoto, P. Adharapurapu, and M.D. Ercegovac, Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XII, 12 pps., 2005.
Variable Radix Real and Complex Digit-Recurrence Division. M.D. Ercegovac and J.-M. Muller,
IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 316-321, 2005.
A Linear-System Operator Based Scheme for Evaluation of Multinomials. P. Adharapurapu and M.D. Ercegovac,
Proc. 17th IEEE Symposium on Computer Arithmetic, pp. 249-256, 2005.
RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementation of On-Line Instructions.
R. McIlhenny and M.D. Ercegovac, IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 275-276, 2005. (Poster)

2004:

Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. J.-A. Pineiro, M.D. Ercegovac,
and J.D. Bruguera. IEEE Trans. Computers, 53(9):1085-1096, 2004.
A Composite Arithmetic Scheme for Evaluation of Multinomials. P. Adharapurapu and M.D. Ercegovac,
Proc. 38th Asilomar Conference on Signals, Systems and Computers, pp. 1889-1893, 2004.
On the Design of an On-Line Complex FIR Filter. R. McIlhenny and M.D. Ercegovac,
Proc. 38th Asilomar Conference on Signals, Systems and Computers, pp. 478-482, 2004.
Complex Square Root with Operand Prescaling. M.D. Ercegovac and J.-M. Muller,
IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 293-303, 2004.
(Best Paper Award)
Design of a complex divider. M.D. Ercegovac and J.-M. Muller,
Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XII, pp. 51-59, 2004.
From the University of Illinois via JPL and UCLA to Vytautas Magnus University - 50 years of computer engineering by Algirdas Avizienis. D. Rennels and M. D. Ercegovac, IFIP Congress Topical Sessions. pp. 175-190, 2004.

2003:

Performance-driven mapping for CPLD architectures. D. Chen, J. Cong, M.D. Ercegovac, and Z. Huang.
IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 22, No. 10, pp. 1424-1431, October 2003.
Comments on "A carry-free 54x54-bit multiplier using equivalent bit conversion". M.D. Ercegovac and T. Lang,
IEEE Journal of Solid-State Circuits, Vol. 38, No. 1, pp. 160-161, 2003.
Left-to-right squarer with overlapped LS and MS parts. M. D. Ercegovac,
Proc. 37th Asilomar Conference on Signals, Systems and Computers, pp. 1451-1455, 2003.
Digit-recurrence algorithms for division and square root with limited precision primitives. M.D. Ercegovac and J.-M. Muller,
Proc. 37th Asilomar Conference on Signals, Systems and Computers, pp. 1440-1444, 2003.
Two-dimensional Signal Gating for Low Power in High-Performance Multipliers. Z. Huang and M.D. Ercegovac,
Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XII, pp. 499-509, 2003.
Complex Division with Prescaling of Operands. M.D. Ercegovac and J.-M. Muller,
IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 293-303, 2003.
High-Radix Iterative Algorithm for Powering Computation. J.-A. Pineiro, M.D. Ercegovac, and J.D Bruguera,
Proc. 16th IEEE Symposium on Computer Arithmetic, pp. 204-211, 2003.
High-performance Left-to-Right Array Multiplier Design. Z. Huang and M.D. Ercegovac,
Proc. 16th IEEE Symposium on Computer Arithmetic, pp. 4-11, 2003.
On-Line High-Radix Exponential with Selection by Rounding. J.-A. Pineiro, M.D. Ercegovac, and J.D Bruguera,
The IEEE International Symposium on Circuits and Systems (ISCAS 2003), pp. 121-124, 2003.

2002:

Reducing the Latency of Division Operations with Partial Caching. E.G. Benowitz, M.D. Ercegovac and F. Fallah. Proc. 36th Asilomar Conference on Signals, Systems and Computers, 2002.
Analysis of Tradeoffs for the Implementation of a High-Radix Logarithm. J.-A. Pineiro, M. D. Ercegovac, and J. D Bruguera,
IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp.132-137, 2002.
Two-dimensional Signal Gating for Low-Power Array Multiplier Design. Z. Huang and M.D. Ercegovac,
The IEEE International Symposium on Circuits and Systems (ISCAS 2002). pp. 489-492, vol.1, 2002.
High-Radix Logarithm with Selection by Rounding. J.-A. Pineiro, M.D. Ercegovac, and J.D. Bruguera,
IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 101-110, 2002.
Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. J.-A. Pineiro, M.D. Ercegovac, and J.D. Bruguera. International Conference on Computer Design - ICCD, Freiburg, Germany, September 2002.
Low Power Array Multiplier Design by Topology Optimization. Z. Huang and M.D. Ercegovac,
Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XII, volume 4791, 2002.
Number Representation Optimization for Low-Power Multiplier Design. Z. Huang and M.D. Ercegovac,
Proc. SPIE on Advanced Signal Processing Algorithms, Architectures, and Implementations XII, volume 4791, 2002.
High-Radix Logarithm with Selection by Rounding. J.-A. Pineiro, M.D. Ercegovac, and J.D. Bruguera,
Proc. IEEE International Conference on Application-Specific Systems, Architectures, and Processors, p. 101-110, 2002.
High-level synthesis with SIMD units. V. Raghunathan, A. Raghunathan, M. Srivastava, M.B. and M.D. Ercegovac,
Proc. ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, p.407-13, 2002.

2001:

FPGA-based library for on-line signal processing. D. Lau, A. Schneider, M.D. Ercegovac, and J.A. Villasenor.
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 28(1-2):129-43,
Kluwer Academic Publishers, May-June 2001.
On Clock-gated Scheme for Low-Power Adders, Z. Huang and M.D. Ercegovac,
Proc. 35th Asilomar Conference on Signals, Systems and Computers, 2001.
On the Design of On-Line Givens Rotation. R. McIlhenny and M.D. Ercegovac,
Proc. 35th Asilomar Conference on Signals, Systems and Computers, 2001.
FPGA Implementation of Pipelined On-line Scheme for 3-D Vector Normalization, Z. Huang and M.D. Ercegovac,
IEEE Symposium on Field-Programmable Custom Computing Machines, 2001.
Performance-Driven Mapping for CPLD Architectures. D. Chen, J. Cong, M.D. Ercegovac, and Z. Huang,
Proc. ACM/SigDA 9th International Symposium on Field-Programmable
Gate Arrays, pp.39 - 43, February 2001.

2000:

Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers. M.D. Ercegovac, T. Lang, J.-M. Muller, and A. Tisserand. IEEE Trans. Computers, 49(7):628-637, 2000.
Improving Goldschmidt Division, Square Root, and Square Root Reciprocal. M.D. Ercegovac, L. Imbert, D.W. Matula, J.-M. Muller, and G. Wei. IEEE Trans. Computers, 49(7):759-762, 2000.
Left-to-Right Carry-Free Scheme for Computing ab+cd. M.D. Ercegovac. 34th Asilomar Conference on Signals, Systems, and Computers, 2000.
BigSky - A Tool for Mapping Numerically Intensive Computations onto Reconfigurable Hardware. R. McIlhenny, Z. Huang, K. Wong, A. Schneider, and M.D. Ercegovac. Proc. 34th Asilomar Conference on Signals, Systems and Computers, 2000.
Effect of Wire Delay on the Design of Prefix Adders in Deep-Submicron Technology. Z. Huang and M.D. Ercegovac. Proc. 34th Asilomar Conference on Signals, Systems and Computers, 2000.
The IEEE Rounding for Multiplier with Redundant Operands. I. Ferguson and M. D. Ercegovac. Proc. 34th Asilomar Conference on Signals, Systems and Computers, 2000.
A component framework for communication in distributed applications. J.M. Fischer and M.D. Ercegovac. Proc. 14th International Parallel and Distributed Processing Symposium IPDPS 2000, p.647-53, 2000.
BigSky - An On-Line Arithmetic Design Tool for FPGAs. A. Schneider, R. McIlhenny, and M.D. Ercegovac. IEEE Symposium on Field-Programmable Custom Computing Machines, 2000.
Fast Evaluation of Elementary Functions with Combined shift-and-add and Polynomial Methods. J.C. Bajard, M.D. Ercegovac, L. Imbert, and F. Rico. Proc. 4th Conference on Real Numbers and Computers (RNC4), Dagstuhl, Germany, 2000.

1999:

On-Line Scheme for Normalizing a 3-D Vector. M.D. Ercegovac and T. Lang.
Proc. 33rd Asilomar Conference on Signals, Systems and Computers, pages 1460-1464, 1999.
A Multiplier with Redundant Operands. M.I. Ferguson and M.D. Ercegovac. Proc. 33rd Asilomar Conference on Signals, Systems and Computers, 1999.
On the Design of an On-line FFT Network for FPGA's. R. McIlhenny and M.D. Ercegovac. 33rd Asilomar Conference on Signals, Systems, and Computers, 1999.
Fast On-Line Multiplication Using LSA Organization. A.F. Tenca, M.D. Ercegovac and M. Louie.
Proc. SPIE on Image Processing Architectures, Digital Signal Processing, volume 3807, 1999.
Low-power behavioral synthesis optimization using multiple precision arithmetic. M.D. Ercegovac, D. Kirovski, M. Potkonjak, Proceedings 1999 Design Automation Conference, pages 568-73, 1999.
FPGA-based Structures for On-Line FFT and DCT. (Extended Abstract) D. Lau, A. Schneider, M.D. Ercegovac, and J. Villasenor. IEEE Symposium on Field-Programmable Custom Computing Machines, pages 310-311, 1999.
On the Design of High-Radix On-Line Division for Long Precision. A.F. Tenca and M.D. Ercegovac.
Proc. 14th IEEE Symposium on Computer Arithmetic, pages 59--66, 1999.

1998:

Long and Fast Up/Down Counters. M.R. Stan, A.F. Tenca, and M.D. Ercegovac.
IEEE Trans. Computers, 47(7):722-735, 1998.
On-line Algorithms for Complex Number Arithmetic. R. McIlhenny and M.D. Ercegovac. Proc. 32nd Asilomar Conference on Signals, Systems, and Computers, 1998.
A variable long-precision arithmetic unit design for reconfigurable coprocessor architectures. A. Tenca and M.D. Ercegovac. Proc. IEEE Symposium on FPGAs for Custom Computing Machines, 1998. IEEE Copyright.
Behavioral Synthesis Optimization Using Multiple Precision Arithmetic. M. D. Ercegovac, D. Kirovski, G. Mustafa, and M. Potkonjak. Proc. IEEE ICASSP, Vol. V, pp.3113-3116, 1998.
Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions
using Small Multipliers. M.D. Ercegovac, T. Lang, J.-M. Muller, and A. Tisserand.
Proc. SPIE on Image Processing Architectures, Digital Signal Processing, volume 3461, pages 543-554, 1998.
Fast Evaluation of Functions at Regularly Spaced Points. M.D. Ercegovac and J.-M. Muller.
Proc. SPIE on Image Processing Architectures, Digital Signal Processing, volume 3461, pages 555-566, 1998.

1997:

A Method of Eliminating Oscillations in High-Speed Recursive Digital Filters. J.S. Fernando and M.D. Ercegovac.
IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, 44(10):861-864, 1997.
On the Implementation of a Three-operand Multiplier. R. McIlhenny and M.D. Ercegovac. 31st Asilomar Conference on Signals, Systems, and Computers, 1997.
Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size. A. Tenca and M.D. Ercegovac. FPGA97 - ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 159-165, Feb. 1997, Monterey.
Effective Coding for Fast Redundant Adders using the Radix-2 Digit Set {0,1,2,3}. M.D. Ercegovac and T. Lang
Proc. 31st Asilomar Conference on Signals, Systems and Computers, pages 1163-1167, 1997.
A High-Radix Multiplier Design for Variable Long-Precision Computations. A.F. Tenca and M.D. Ercegovac.
Proc. 31st Asilomar Conference on Signals, Systems and Computers, pages 1173-1177, 1997.

1996:

On Recoding in Arithmetic Algorithms. M.D. Ercegovac and T. Lang. J. of VLSI Signal Processing, 14:283--294, 1996.
Vector Quantization with Variable-Precision Classification. R. Dionysian and M.D. Ercegovac. IEEE Trans. on Image Processing, 5(11):1528--1538, 1996.
Vector quantization with compressed codebooks. R. Dionysian and M.D. Ercegovac.
Image Communications, 9:79--88, 1996.
Input Synchronization in Low Power CMOS Arithmetic Circuit Design. C. Fabian and M.D. Ercegovac. 30th Asilomar Conference on Signals, Systems, and Computers, 1996.
On Using 1-out-of-n Codes for (p,q) Counter Implementations. R. McIlhenny and M.D. Ercegovac. 30th Asilomar Conference on Signals, Systems, and Computers, 1996. IEEE Copyright.
Design of high-radix digit-slices for on-line computations. A. Tenca and M.D. Ercegovac. SPIE Conference on High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, 1996.

1995:

A variable-precision square root implementation on field programmable gate arrays.
M. Louie and M.D. Ercegovac. The Journal of Supercomputing, 9:315--336, 1995.
On Reducing Transition Counts in Sign Detection Circuits. M.D. Ercegovac, C. Fabian and T. Lang. 29th Asilomar Conference on Signals, Systems, and Computers, 1995.
TSIM Manual, version 1. C. Fabian. UCLA Computer Science Department Technical Report, 1995.
Sign detection and comparison networks with small number of transitions. M.D. Ercegovac and T. Lang.
Proc. 12th IEEE Symposium on Computer Arithmetic, pages 59--66, 1995.
FPGA implementation of polynomial evaluation algorithms. M.D. Ercegovac, J.M. Muller, and A.Tisserand.
Proc. SPIE on Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, volume 2607, pages 177--188, 1995.
Low-Power Accumulator (Correlator). M.D. Ercegovac and T. Lang, Proc. 1995 IEEE Symposium on Low Power Electronics, pages 30--31, San Diego, 1995.

1994:

Implementing division with field programmable gate arrays. M. Louie and M.D. Ercegovac.
Journal of VLSI Signal Processing, 7:271--285, 1994.
Very-high radix division with prescaling and selection by rounding. M.D. Ercegovac, T. Lang, and P. Montuschi.
IEEE Trans. Comput., 43(8):909--918, August 1994.
Conventional and on-line arithmetic designs for high-speed recursive digital filters. J.S. Fernando and M.D. Ercegovac. Journal of VLSI Signal Processing, 7:189--197, 1994.
Reducing transition counts in arithmetic circuits. M.D. Ercegovac and T. Lang.
Proc. 1994 IEEE Symposium on Low Power Electronics, pages 67--68, San Diego, 1994.
On recoding in arithmetic algorithms. M.D. Ercegovac and T. Lang.
Proc. 28th Asilomar Conference on Signals, Systems and Computers, 1994.
A method of eliminating oscillations in high-speed recursive filters. J. Fernando and M.D. Ercegovac.
Proc. 1994 IEEE Workshop on VLSI Signal Processing, 1994.
Multiplication and inner product with field programmable gate arrays. M. Louie and M.D. Ercegovac.
Proc. 1994 IEEE Workshop on VLSI Signal Processing, 1994.
A variable precision multiplier for field programmable gate arrays. M. Louie and M.D. Ercegovac.
Proc. 2nd International ACM/SIGDA Workshop on Field-Programmable Gate Arrays, 1994.

1993:

Multiplication/division/square root module for massively parallel computers. M.D. Ercegovac and T. Lang.
Integration, the VLSI Journal, 16:221--234, 1993.
Very high radix division with selection by rounding and prescaling. M.D. Ercegovac, T. Lang, and P. Montuschi.
Proc. 11th IEEE Symposium on Computer Arithmetic}, pages 112--119, 1993.
Symbolic synthesis of parallel processing systems. J.J. Liu and M.D. Ercegovac.
Proc. 7th International Parallel Processing Symposium, 1993.
A digit-recurrence square root implementation for field programmable gate arrays. M. Louie and M.D. Ercegovac.
Proc. IEEE Workshop on FPGAs for Custom Computing Machines, pages 178--183, 1993.
On digit-recurrence division implementations for field programmable gate arrays. M. Louie and M.D. Ercegovac.
Proc. 11th IEEE Symposium on Computer Arithmetic, pages 202--209, 1993.

1992:

A methodology for performance analysis of parallel computations with looping constructs. A. Kapelnikov,
R.R. Muntz, and M.D. Ercegovac. J. of Parallel and Distributed Computing, 14(3):105--120, March 1992.
Architectural support for goal management in flat concurrent Prolog. L. Alkalaj, T. Lang, and M.D. Ercegovac.
Computer, 25(8):34--47, August 1992.
On-the-fly rounding. M.D. Ercegovac and T. Lang. IEEE Trans. Comput., Vol. 41(12):1497--1503, Dec. 1992.
Conventional and on-line arithmetic designs for high-speed recursive digital filters.
J. Fernando and M.D. Ercegovac. Proc. IEEE Workshop on VLSI Signal Processing}, pages 81--90, 1992.
On-line arithmetic modules for recursive digital filters. J. Fernando and M.D. Ercegovac.
Proc. 26th Asilomar Conference on Signals, Systems, and Computers, 1992.
Variable precision representation for efficient VQ codebook storage. R. Dionysian and M.D. Ercegovac.
Proc. of Data Compression Conference DCC'92, pages 319--328, 1992.
Fast arithmetic for recursive computations. M.D. Ercegovac and T. Lang.
Proc. IEEE Workshop on VLSI Signal Processing, pages 14--28, 1992.
Multiplication/division module for massively parallel computers. M.D. Ercegovac and T. Lang.
Proc. SPIE, Advanced Signal Processing Algorithms, Architectures, and Implementations, pages 110--117, San Diego, 1992.
MAMACG: A tool for automatic mapping of matrix algorithms onto mesh array computational graphs.
D. Le, M. Ercegovac, T. Lang, and J. Moreno.
Proc. 1992 Application Specific Array Processors, pages 511--525. IEEE Computer Society Press, 1992.
Mapping division algorithms to field programmable gate arrays. M. Louie and M. Ercegovac.
Proc. 26th Asilomar Conference on Signals, Systems, and Computers, 1992.

1991:

Module to perform multiplication, division and square root in systolic arrays for matrix computations.
M.D. Ercegovac and T. Lang. J. Parallel and Distributed Computing, 11(3):212--221, March 1991.
Evaluation of two-summands adders implemented in ECDL CMOS differential logic. S.-L. Lu and M. D. Ercegovac.
IEEE J. of Solid-State Circuits, 26(6):1152--1160, August 1991.
Gate array implementation of on-line algorithms for floating-point operations. P.K.-G. Tu and M.D. Ercegovac.
J. of VLSI Signal Processing, (3):307--317, 1991.
On the implementation of a parallel algorithm for higher radix division.
M.D. Ercegovac, T. Lang, and P. Montuschi. Proceedings IEEE COMPEURO '91, pages 603--607, 1991.
Application of on-line arithmetic algorithms to the SVD computation: Preliminary results.
P.K. Tu and M.D. Ercegovac. Proc. 10th IEEE Arithmetic Symposium, pages 246--255, 1991.

1990:

A novel CMOS implementation of double-edge-triggered flip-flops. S.-L. Lu and M. D. Ercegovac.
IEEE Journal of Solid-State Circuits, 25(4):1008--1009, August 1990.
Simple radix-4 division with operands scaling. M.D. Ercegovac and T. Lang.
IEEE Trans. Comput., Vol. C-39(9):1204--1207, Sept. 1990.
Redundant and on-line CORDIC: Application to matrix triangularization and SVD. M.D. Ercegovac and T. Lang.
IEEE Trans. Comput., 39(6):725--740, June 1990.
Radix-4 square root without initial PLA. M.D. Ercegovac and T. Lang.
IEEE Trans. Comput., Vol. C-39(8):1016--1024, Aug. 1990.
Fast multiplication without carry-propagate addition. M.D. Ercegovac and T. Lang.
IEEE Trans. Comput., C-39(11):1385--1390, November 1990.
Variable precision linear classifier. R. Dianysian and M.D. Ercegovac.
Proc. VLSI Signal Processing, pages 124--131. IEEE Press, 1990.
Architectural support for the management of tightly-coupled fine-grain goals in flat concurrent Prolog.
L. Alkalaj, T. Lang, and M.D. Ercegovac.
Proc. 17th International Symposium on Computer Architecture, pages 292--301, 1990.
Gate array implementation of on-line algorithms for floating-point operations. P.K. Tu and M.D. Ercegovac.
Proc. 24th Asilomar Conference on Signals Circuits and Computers, 1990.

1989:

A modeling methodology for the analysis of concurrent systems and computations. A. Kapelnikov, R.R. Muntz, and M.D. Ercegovac. Journal of Parallel and Distributed Computing, 6:568--597, 1989.
Fast radix-2 division with quotient-digit prediction. M.D. Ercegovac and T. Lang.
J. of VLSI Signal Processing, 2(1):169--180, Jan. 1989.
Binary counter with counting period of one half adder independent of counter size. M.D. Ercegovac and T. Lang.
IEEE Transactions on Circuits and Systems, 36(6):924--926, June 1989.
Most-significant-digit-first and on-line arithmetic approaches for the design of recursive filters.
M.D. Ercegovac and T. Lang. Proc. 23rd Asilomar Conference on Signals, Systems and Computers, pages 7--11, 1989.
On-line arithmetic for DSP applications. M.D. Ercegovac and T.Lang.
Proc. 32nd IEEE Midwest Symposium on Circuits and Systems, 1989.
On-the-fly rounding for division and square root. M.D. Ercegovac and T. Lang.
Proc. 9th IEEE Symposium on Computer Arithmetic, pages 169--173, 1989.
Radix-4 square root without initial PLA. M.D. Ercegovac and T. Lang.
Proc. 9th IEEE Symposium on Computer Arithmetic, pages 162--168, 1989.
Design of an on-line multiply-add module for recursive digital filters.
R.H. Brackert, M.D. Ercegovac, and A.N. Willson.
Proc. 9th IEEE Symposium on Computer Arithmetic, pages 34--41, 1989.
Recursive filter using on-line arithmetic. R.H. Brackert, A.N. Willson, and M.D. Ercegovac.
Proc. IEEE International Symposium on Circuits and Systems, pages 1552--1556, 1989.
Using simulation and Markov modeling to select data flow threads. D.R. Greening and M.D. Ercegovac.
Proceedings IPCCC, 1989.
Design of on-line division unit. P. Tu and M.D. Ercegovac.
Proc. 9th IEEE Symposium on Computer Arithmetic, pages 42--49, 1989.

1988:

On-line scheme for computing rotation factors. M.D. Ercegovac and T. Lang.
J. Parallel and Distributed Computing, 5(6):209--227, June 1988.
Heterogeneity in supercomputer architectures. M.D. Ercegovac. Parallel Computing, 7:367--372, September 1988.
Implementation of an SVD processor using redundant CORDIC. M.D. Ercegovac and T. Lang.
Proc. SPIE Conference on Real-Time Signal Processing, San Diego, 1988.
Implementation of fast angle calculation and rotation using on-line CORDIC. M.D. Ercegovac and T. Lang.
Proc. 1988 IEEE International Symposium on Circuits and Systems, Helsinki, Finland, 1988.
On-line arithmetic: A design methodology and applications. M.D. Ercegovac and T. Lang.
Proc. VLSI Signal Processing, pages 252--263, 1988.
Implementation of fast radix-4 division with operands scaling. M.D. Ercegovac, T. Lang, and R. Modiri.
Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors, New York, 1988.

1987:

On-the-fly conversion of redundant into conventional representations. M.D. Ercegovac and T. Lang.
IEEE Trans. Comput., Vol. C-36(7):895--897, July 1987.
Fast cosine/sine algorithm using on-line CORDIC. M.D. Ercegovac and T. Lang.
Proc. IEEE Asilomar Conference on Signals, Systems, and Computers, 1987.
Fast radix-4 multiplication without carry-propagate addition. M.D. Ercegovac and T. Lang.
Proc. ICCD '87 Conference, New York, 1987.
On-line scheme for computing rotation factors. M.D. Ercegovac and T. Lang.
Proc. 8th IEEE Symposium on Computer Arithmetic, 1987.
On-line schemes for computing rotation angles for SVDs. M.D. Ercegovac and T. Lang.
Proc. SPIE Conference on Real-Time Signal Processing, San Diego, 1987.
A dynamic memory management policy for fp. L. Alkalaj, M.D. Ercegovac, and T. Lang.
Proc. 1987 Hawaii International Conference on Systems Science, 1987.
An area-time efficient binary divider. M.D. Ercegovac, T. Lang, J.G. Nash, and L.P. Chow.
Proc. ICCD '87 Conference, New York, 1987.
A methodology for the performance evaluation of distributed computations.
A. Kapelnikov, R.R. Muntz, and M.D. Ercegovac.
Proc. IFIP Conference on Distributed Processing, October, 1987.
Implementation of a serial/parallel multiplier and divider on a systolic chip.
J.G. Nash, L.W. Chow, M.D. Ercegovac, and T. Lang.
Proc. IEEE Asilomar Conference on Signals, Systems, and Computers, 1987.
Static allocation for a dataflow multiprocessor system.
T.M. Ravi, M.D. Ercegovac, T. Lang, and R.R. Muntz.
Proc. 2nd International Conference on Supercomputing, pages 169--178, Santa Clara, 1987.
A radix-4 on-line division algorithm. P.K. Tu and M.D. Ercegovac.
Proc. 8th IEEE Symposium on Computer Arithmetic, 1987.

1986:

Design and implementation of an on-line algorithm. D. Tullsen and M.D. Ercegovac.
Proc. SPIE Conference on Real-Time Signal Processing, San Diego, August 1986.

1985:

Performance analysis of variable resolution dataflow systems. J.L. Gaudiot and M.D. Ercegovac.
J. of Parallel and Distributed Systems, November 1985.
A division algorithm with prediction of quotient digits. M.D. Ercegovac and T. Lang.
Proc. IEEE 7th Symposium on Computer Arithmetic, pages 51--56, Urbana, Illinois, 1985.
A functional language for description and design of digital systems: Sequential constructs.
F. Meshkinpour and M.D. Ercegovac. Proc. IEEE Proc. of the 22nd ACM/IEEE Design Automation Conference, pages 238--244, 1985.
vfp: An environment for the multi-level specification, analysis, and synthesis of hardware algorithms.
D.R. Patel, M. Schlag, and M.D. Ercegovac. Proc. Conference on Functional Programming Languages and Computer Architecture, pages 238--255, Nancy, France, 1985. Springer-Verlag, Lecture Notes 201.

1984:

Fault-tolerance in binary tree architectures. C.S. Raghavendra, A. Avizienis, and M.D. Ercegovac.
IEEE Trans. Comput., Vol. C-33(6):568--571, June 1984.
On-line arithmetic: An overview. M.D. Ercegovac. SPIE Vol. 495 Real-Time Signal Processing VII,
pages 86--93, 1984.
Task partitioning, allocation and simulation for a dataflow multimicroprocessor system.
M.D. Ercegovac, P.K. Chan, Z.~Konstantinovic, T.M. Ravi, and M.D.F. Schlag.
Proc. Summer Computer Simulation Conference, 1984.
A dataflow multimicroprocessor architecture for high-speed simulation of continuous systems.
M.D. Ercegovac, P.K. Chan, and T.M. Ravi. Proc. International Workshop on High-Level Architecture, 1984.
On a dataflow approach in high-speed simulation of continuous systems. M.D. Ercegovac and W.J. Karplus.
Proc. International Workshop on High-Level Architecture, 1984.
An experimental performance evaluation of a data-flow computer using variable resolution actors.
J.L. Gaudiot and M.D. Ercegovac. Proc. of Phoenix Conference on Communications and Computers, 1984.
Performance analysis of a data-flow computer with variable resolution actors. J.L. Gaudiot and M.D. Ercegovac.
Proc. of the 1984 International Conference on Distributed Processing, 1984.

1983:

Error analysis of certain floating-point on-line algorithms. O. Watanuki and M.D. Ercegovac.
IEEE Trans. Comput., C-32(4):352--358, April 1983.
A functional language architecture for high-speed digital simulation. M.D. Ercegovac and S.L. Lu.
Proc. 1983 Summer Computer Simulation Conference, July 11-13, 1983.
A VLSI design of an area-time efficient multiplier. M.D. Ercegovac and G.J. Nash.
Proc. International Conference on Computer Design - VLSI in Computers, New York, 1983.
Functional language and data flow architectures. M.D. Ercegovac, D.R. Patel, and T. Lang.
Proc. 1983 Summer Computer Simulation Conference, Vancouver, 1983.
A survey of floating-point arithmetic implementations. M.D. Ercegovac.
Proceedings 1983 SPIE Conference on Real-Time Signal Processing, 1983.
Simulation of a data-flow machine using the SARA system. J.L. Gaudiot and M.D. Ercegovac.
Proc. 17th Asilomar Conference on Circuits, Systems and Computers, 1983.
On-line multiplicative normalization. A.L. Grnarov and M.D. Ercegovac.
Proceedings of the 6-th IEEE Symposium on Computer Arithmetic, Aarhus, Denmark, 1983.
General approaches for achieving high speed computations. T. Lang and M.D. Ercegovac.
Proc. 1983 Summer Computer Simulation Conference, Vancouver, 1983.
Fault tolerance in binary tree architectures. C.S. Raghavendra, A.A. Avizienis, and M.D. Ercegovac.
1983 International Symposium on Fault-Tolerant Computing, Milan, Italy, 1983.

1982:

An on-line square root algorithm. V.G. Oklobdzija and M.D. Ercegovac.
IEEE Trans. Comput., Vol. C-31(1):70--75, Jan. 1982.
On reducing storage requirements of table-lookup multiplication. M.D. Ercegovac and P.K. Chan.
Proc. 16th Asilomar Conference on Circuits, Systems and Computers, November 8-10 1982.
A scheme for handling arrays in data-flow systems. J.L. Gaudiot and M.D. Ercegovac.
Proc. 3rd International conference on Distributed Computer Systems, 1982.
Testability enhancement of VLSI using circuit structures. V.G. Oklobdzija and M.D. Ercegovac.
Proc. IEEE 1982 International Conference on Circuits and Computers, New York, 1982.

1981:

Floating-point on-line arithmetic: Algorithms. O. Watanuki and M.D. Ercegovac.
Proc. 5th IEEE Symposium on Computer Arithmetic, pages 81--86, 1981.
Floating-point on-line arithmetic: Error analysis. O. Watanuki and M.D. Ercegovac.
Proc. 5th IEEE Symposium on Computer Arithmetic, pages 87--91, 1981.
The queue machines: An organization for parallel computation. M. Feller and M.D. Ercegovac.
Proc. CONPAR '81, Lecture Notes No. 111}, pages 37--47. Springer-Verlag, 1981.
Status and trends in the development of supercomputers in the U.S. M.D. Ercegovac.
Proc. International Conf. DATASHOW '81, September 1981.
Design of a digit-slice on-line arithmetic unit. A. Gorji-Sinaki and M.D. Ercegovac.
Proc. 5th IEEE Symposium on Computer Arithmetic, pages 72--80, 1981.
Fast multiplication schemes for microprocessor applications. A.L. Grnarov, C.S. Raghavendra,
and M.D. Ercegovac. Proc. Int. Conf. on Microcomputer Applications to Industrial Control, 1981.
A simulator for on-line arithmetic. C.S. Raghavendra and M.D. Ercegovac.
Proc. 5th IEEE Symposium on Computer Arithmetic, pages 72--80, 1981.

1980:

On the performance of on-line arithmetic. M.D. Ercegovac and A.L. Grnarov.
Proc. Int. Conf. on Parallel Processing, 1980.
A multi-processor bit-slice organization for function evaluation. M.C. Chu and M.D. Ercegovac.
Proc. Int. Conf. on Mini and Micro Computers, 1980.
VLSI-oriented iterative networks for array computations. A.L. Grnarov and M.D. Ercegovac.
Proc. 1980 IEEE Conf. on Circuits and Computers, pages 60--64, 1980.

1979:

Reply on 'comments on A fast Gray-to binary conversion'. M.D. Ercegovac.Proc. of the IEEE, 67(3):444--445, March 1979.
An algorithm for on-line normalization. A.L. Grnarov and M.D. Ercegovac
UCLA Comp. Sci. Dept. Quarterly, volume~7, pages 81--93, July 1979.

1978:

A fast Gray-to-binary code conversion. M.D. Ercegovac. Proc. of the IEEE, 66(4):524--552, April 1978.
An on-line square root algorithm. M.D. Ercegovac.
Proc. of the 4th IEEE Symposium on Computer Arithmetic, pages 183--189, 1978.
An arithmetic module for efficient evaluation of functions. M.D. Ercegovac and M. Takata.
Proc. of the 4th IEEE Symposium on Computer Arithmetic, pages 190--199, 1978.
A study of standard building blocks for the design of fault-tolerant distributed computer systems.
D.A. Rennels, A. Avizienis, and M.D. Ercegovac. Proc. of the FTCS 8, 1978.

1977:

A general hardware-oriented method for evaluation of functions and computations in a digital computer.
M.D. Ercegovac. IEEE Trans. Comput., C-26(7):667--680, July 1977.
On-line algorithms for division and multiplication. K.S. Trivedi and M.D. Ercegovac.
IEEE Trans. Comput., C-26(7):681--687, July 1977.
An Investigation of Fault-Tolerant Architecture For Large Scale Numerical Computing.
Avizienis, A., Ercegovac, M.D., Lang, T., Sylvain, P., Thomasian, A. Proc. Conference on High Speed Computer and Algorithm Organization, University of Illinois, Academic Press, 1977.

1976:

An approach in reducing complexity of numerical computations. M.D. Ercegovac.
Algorithms and Complexity; New Directions and Recent Results, page 452. Academic Press, 1976.
(Abstract).

1975:

A general method for evaluation of functions and computations in digital computer. M.D. Ercegovac.
Proc. of the 3rd IEEE Symposium on Computer Arithmetic, pages 147--157, 1975.
On-line algorithms for division and multiplication. K.S. Trivedi and M.D. Ercegovac.
Proc. of the 3rd IEEE Symposium on Computer Arithmetic, pages 161--167, 1975.

1973:

Radix-16 evaluation of certain elementary functions. M.D. Ercegovac.
IEEE Trans. Comput., Vol. C-22(6):561--566, June 1973.